Project Description

The development kit of DSX50WZ board combines XC3S50AN Spartan-3AN and WIZnet W5300.
This small factor board may be configured as a very efficient web server and still has most of the XC3S50 FPGA resources available for your application.If you are starting a new project with FPGA connected to Ethernet, want to learn FPGA or just need a web server/network connection.

The block Diagram of DSX50WZ is as shown below.



Feature Description
FPGA Spartan-3 XC3S50AN from Xilinx
• 50k system gates, 1,584 Logic Cells, 1,408 CLB Flip-Flops
• 54k bits of Block RAM bits in 3 blocks
• 627k bits of User Flash
• 2 Digital Clock Managers
Ethernet W5300 from WIZnet
• Hardwired TCP/IP Protocols: TCP, UDP, ICMP, Ipv4,,ARP, IGMPv2, PPPoE Ethernet
• 8 independent SOCKETs simultaneously
• Internal 128k bytes memory for RX /TX buffers
• Embedded 10BaseT/100BaseT Ethernet PHY
Miscellaneous • 50.000 MHz clock generator with extremely low jitter, frequency,resolution to six decimal places and stabilities +/- 20 PPM
• 1k bit UNI/O EEPROM for storing MAC and IP address
• MAX3232 RS232 driver
• 2 LEDs
• PicoBlaze soft processor core from Xilinx running with 100MHz clock
Power • Power Supply 3.5 – 6.0 VDC
• Power consumption under 1Watt
• On board high efficiency switching step down converter TPS65053
• W5300 power switchable under XC3S50 control
Connectors • RJ45 Ethernet
• DSUB-9 for RS232
• 3 pin header for power supply
• optional three 24 pin headers/sockets (0.1 spacing)• optional micro SD card connector
Dimensions • 3.7″ x 1.5″ (94 x 38 mm)
Network Performance • 8.0 MByte/s measured when uploading 1 GB file using HTTP POST metod in 125 seconds.• 4.8 MByte/s measured when serving 1 GB file using HTTP GET metod in 208 seconds.• 62ms time to serve this page (request for 15 files, tx/rx 219 packets, Mozilla Firefox browser on Windows XP).



Source exmaple code :
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