Atmel’s low-cost gateway (LCGW) reference design – powered by the ATmega256RFR2 – is a turn-key production-ready solution that connects IEEE 802.15.4 wireless networks to wired Ethernet networks. This gateway allows IEEE 802.15.4 wireless devices to link with mobile devices such as smartphones and tablets running remote-control applications.
“The ATmega256RFR2 wireless system-on-a-chip (SoC) combines best-in-class radio performance with the efficient Atmel AVR 8-bit CPU,” an Atmel engineering rep told Bits & Pieces. “In short, the ATmega256RFR2 provides a responsive CPU and high-performance radio to address the demanding tasks of network coordinator and data concentrator.”
Meanwhile, the WIZnet W5200 embedded Ethernet controller features a 10BaseT/100BaseTX MAC and PHY, supporting numerous popular Ethernet protocols including TCP/IP, UDP and IPv4.
“Essentially, the wired Ethernet interface is a low-cost, reliable and secure connection that works with the end user’s existing routers, access-points, WLANs and ISPs,” the engineering rep continued. “Remember, wired Ethernet lowers cost and also avoids interference problems and regulatory issues inherent with co-located radio solutions.”
The engineering rep also noted that the reference design was formulated with low BOM cost as a primary objective. As such, the design is free of superfluous accessories and non-essential sub-systems, with a standard JTAG interface provided for programming and debug.
Atmel’s design includes optional EEPROM and Data-Flash memory sockets, while DC power is derived from a USB Micro-B Dedicated Charge Port (DCP) – allowing users to power the gateway with common phone chargers or from Wi-Fi Access Points via USB ports. As expected, both the USB and Ethernet connections have ESD/EMI suppression to improve reliability.
In terms of operation, connections to the LCGW are relatively simple. Connect the DCP to a USB power source using the Micro-B connector and D3 will light indicating DC power is ready. Then, connect the RJ45 Ethernet port to a router with a CAT5 patch cable.
“Atmel’s ATmega256RFR2 can be programmed and debugged using the 10-pin JTAG header and Atmel JTAGICE programmers. SW2 is a hardware RESET for the CPU, while Ethernet MAC Reset is driven by software,” the engineering rep explained. “And J5 exposes the power rails for testing. There are several user defined features: UART0, Port F GPIO, SW1 and D1 are uncommitted and available to the application developer.”
On the CPU side, Atmel’s ATmega256RFR2 is a low-power CMOS 8-bit microcontroller based on AVR enhanced RISC architecture combined with a high data rate transceiver for the 2.4GHz ISM band. By executing powerful instructions in a single clock cycle, the device achieves throughputs approaching 1 MIPS per MHz allowing system designers to optimize power consumption versus processing speed. Meanwhile, the radio transceiver provides high data rates from 250kb/s up to 2Mb/s, frame handling, outstanding receiver sensitivity and high transmit output power enabling a very robust wireless communication.
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