Project Description


This development board provides schematics, MODBUS-TCP original code (ARM, FPGA), and provides complete technical support. The full development video of the FPGA is included.

The expansion board is sold separately:

The development board adopts ARM+FPGA+Ethernet structure, has modularity and can be used as a core board. After practice, it has strong stability and reliability.

ARM adopts the popular CORTEX-M3 series MCU–STM32F205. The STM32F205 belongs to the CORTEX-M3 series MCU, and its frequency is raised to 120MHz. Compared with the STM32F10X series, the performance is further improved.

The FPGA adopts FLEL architecture-based ACTEL ProASIC3 series FPGA-A3P250Q208, which has similar programmable resources to Altera’s EP1C3 (Cyclone1), EPM2210 (CPLD) and XILINX XC2S150, XC3S200 and XCV150. The A3P250 is part of the ProASIC3 family of FPGAs. The ProASIC3 family of Flash-based FPGAs, including ProASIC3/E, ProASIC3 nano and ProASIC3L, delivers breakthroughs in power, price, performance, density and features for today’s most demanding high volume applications. In addition to providing commercial and industrial temperature devices to support portable, consumer, industrial, communications and medical applications, Actel offers specially selected automotive and **ProASIC3 FPGA products.

Features :

  1. Low power consumption, very limited power-on current surge, no large current transition period, and maximum energy saving. These two phenomena exist in most FPGAs. Provides low dynamic power consumption.

  2. cost optimization, reprogrammable, non-volatile storage, power-on and use.

  3. using the inherent advantages of 128-bit Flash lock and Flash technology to provide the most robust security protection for programmable logic design

  4. enhanced I / O structure

  5. Immunity with loss of configuration data caused by atmospheric neutrons (firmware error)

  6. provide car (T-Grade) and ** temperature level products
    The network chip adopts W5300 chip, internal integrated hardware TCP/IP core, supports 100M/10M Ethernet, fast communication speed and simple programming.

Program description:

In the development practice of multiple products, I found that for industrial product development, it is generally not desirable to increase the CPU speed to meet the functional requirements, which will bring about a substantial increase in design costs, so it is more important for electronic engineers to design from the product. The structure and program optimization optimizes product performance. The routines of this experiment board are written by themselves, from the initial register definition to the implementation of some of the function functions, and the function library provided by the original ST company is not used, which is beneficial to understand the detailed process of different register configurations and deepen the learning effect. Conducive to the optimization of future programs.

The original program of A3P250 and the original program of STM32F205 are included in the “original program” file. The program of A3P250 is opened with Libero Soc v10.0, and the program of STM32F205 is opened with KEIL v4.34.

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